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Schematic gallery¶

The images in this section are bit-mapped PNG images with DPI=300. Higher quality images can be generated using PDF or PGF formats.

Circuits¶

E1.sch

V1 1 0_1; down
R1 1 2 R_s; right=1.5
C1 2 0; down, v=v_C
W 0_1 0; right
W 0 0_2; right
R2 2_2 0_2 R_in; down, v=v_{in}
W 2 2_2; right
E1 3 0_3 2 0 A; down, l=A v_{in}
R3 3 4 R_out; right=1.5
R4 4 0_4 R_L; down
W 0_2 0_3; size=1.2
W 0_3 0_4
P1 4 0_4; down
; label_ids=False, draw_nodes=connections, label_nodes=False
_images/E1.png

F1.sch

V1 1 0_1; down
R1 1 2 R_s; right=1.5
C1 2 0; down, v=v_C
W 0_1 0; right
W 0 0_2; right
R2 2_2 0_2 R_in; down, v=v_{in}
W 2 2_2; right
F1 3 0_3 V1 F; down, l=F i_{in}
R3 3 4 R_out; right=1.5
R4 4 0_4 R_L; down
W 0_2 0_3; size=1.2
W 0_3 0_4
P1 4 0_4; down
; label_ids=False, draw_nodes=connections, label_nodes=False
_images/F1.png

G1.sch

V1 1 0_1; down
R1 1 2 R_s; right=1.5
C1 2 0; down, v=v_C
W 0_1 0; right
W 0 0_2; right
R2 2_2 0_2 R_in; down, v=v_{in}
W 2 2_2; right
G1 3 0_3 2_2 0 F; down, l=G v_{in}
R3 3 4 R_out; right=1.5
R4 4 0_4 R_L; down
W 0_2 0_3; size=1.2
W 0_3 0_4
P1 4 0_4; down
; label_ids=False, draw_nodes=connections, label_nodes=False
_images/G1.png

H1.sch

V1 1 0_1; down
R1 1 2 R_s; right=1.5
C1 2 0; down, v=v_C
W 0_1 0; right
W 0 0_2; right
R2 2_2 0_2 R_in; down, v=v_{in}
W 2 2_2; right
H1 3 0_3 V1 F; down, l=H i_{in}
R3 3 4 R_out; right=1.5
R4 4 0_4 R_L; down
W 0_2 0_3; size=1.2
W 0_3 0_4
P1 4 0_4; down
; label_ids=False, draw_nodes=connections, label_nodes=False
_images/H1.png

K2.sch

V 4 5 ac; down
W 4 1; right
W 5 0; right
L1 1 0; down
L2 2 3; down=1.5
K1 L1 L2; size=1.5
W 2 6; right
W 3 7; right
C 6 7; down
;label_ids=false
_images/K2.png

VRL2.sch

V1 1 0 step; down
R1 1 2; left=2, i=I_1, v=V_{R_1}
R2 1 3; right=2, i=I_2, v=V_{R_2}
L1 2 0_1; down=2, i=I_1, v=V_{L_1}
L2 3 0_3; down=2, i=I_2, v=V_{L_2}
W 0 0_3; right
W 0 0_1; left
_images/VRL2.png

VRmesh1.sch

V1 0 1;up=2, v=V
V2 0 3;right=2, v=V
V3 0 5;down=2, v=V
V4 0 7;left=2, v=V
R1 1 2;right=2, v=V
R2 3 2;up=2, v=V
R3 3 4;down=2, v=V
R4 5 4;right=2, v=V
R5 5 6;left=2, v=V
R6 7 6;down=2, v=V
R7 7 8;up=2, v=V
R8 1 8;left=2, v=V
_images/VRmesh1.png

cmos-esd-damage.sch

C1 1 0 100e-12;down, size=1.5, v={5\,kV}
R1 1 6 1500;right
R2 2 4 1e12;down
C2 3 5 5e-12;down
W 2 3;right
W 0 4;right
W 4 5;right
SW 6 2 no;right, l=, size=1.5
;;\node[blue,draw,dashed,inner sep=5mm,anchor=north, fit=(1) (6) (0), label=Human body model] {};
;;\node[blue,draw,dashed,inner sep=5mm, fit=(2) (3) (4) (5), label=CMOS input model]{};
;draw_nodes=connections, label_nodes=False, label_ids=False
_images/cmos-esd-damage.png

cmos-input-model1.sch

P PIO GND; down
W PIO 1; right
W GND 3; right
D1 1 2; up
D2 3 1; up
W 1 4; right
W 4 5; up, size=0.25
W 4 6; down, size=0.25
M1 7 5 8 pmos; right
M2 7 6 9 nmos; right
W 3 9; right
W 2 8; right
W 7 10; right, size=0.25
W 8 11; right
W 9 12; right
VDD 11 12;down
; draw_nodes=connections, label_nodes=alpha
_images/cmos-input-model1.png

cmos-led1.sch

U1 buffer; right
W U1.out 1; right=0.5
R 1 2; right=2, i>^=I_o
D 2 0_2 led; down, v=V_f, l={}
W U1.vss 0_3; down
W 0_3 0_1; right
W 0_1 0_2; right
O 1 0_1; down, v=V_o
W 0_3 0; down=0.1, 0V
W U1.vdd _vdd; up=0.3, implicit, l=V_{DD}
; draw_nodes=connections, label_nodes=false
_images/cmos-led1.png

cmos-open-drain.sch

M 1 2 3; right, l=Pull-down (NMOS)
W 3 0; down=0.1, sground, l=$V_{SS}
W 1 4; right
W 4 5; right
R 4 6; up, l=External pull-up
W 6 7; up=0.1, sground, l=$V_{DD}
;draw_nodes=connections, label_nodes=False, label_ids=False
_images/cmos-open-drain.png

cmos-protection1.sch

U1 inverter; right, size=1.5
R 2 U1.in; right
D1 2 3; up
D2 4 2; up
W 1 2; right=0.5
#; help_lines=0.05
_images/cmos-protection1.png

cmos-totem2.sch

M1 1 2 3 pmos; right, l=Pull-up (PMOS)
M2 1 4 5 nmos; right, l=Pull-down (NMOS)
W 3 6; up=0.1, sground, l=V_{DD}
W 5 7; down=0.1, sground, l=V_{SS}
W 1 11; right=2
W 11 PIN; right, output, l=PIN
D1 11 12; up
W 12 12_1; up=0.1, implicit, l=V_{DD}
D2 13 11; up
W 13 13_1; down=0.1, implicit, l=V_{SS}

;draw_nodes=connections, label_nodes=alpha, label_ids=False
_images/cmos-totem2.png

cmos_C_load_thevenin.sch

U1 inverter; right, fill=blue!50, l
W U1.vss 0; down, color=blue
W U1.out 1; right=0.5, color=blue, i=I_o
W 0 0_1; right=0.5, color=blue
P 1 0_1; down, v=V_o
W 1 1_1; right
Cl 1_1 0_2; down, v=V_l
W 0_1 0_2; right
Rt 1_1 1_2; right=2
Vt 1_2 0_3; down
W 0_2 0_3; right
; draw_nodes=connections, label_nodes=none, color=blue
_images/cmos_C_load_thevenin.png

cmos_R_series_C_load_thevenin.sch

U1 inverter; right, fill=blue!50, l
W U1.vss 0; down
W U1.out 1; right=0.5, i=I_o
W 0 0_1; right=0.5
P 1 0_1; down, v=V_o
Rs 1 1_1; right=2
Cl 1_1 0_2; down, v=V_l
W 0_1 0_2; right
Rt 1_1 1_2; right=2
Vt 1_2 0_3; down=1.5
W 0_2 0_3; right
; draw_nodes=connections, label_nodes=none
_images/cmos_R_series_C_load_thevenin.png

common-base.sch

Q1 3 0_2 2 pnp; up
W 0_2 0; down=0.25
R1 1 2;right
R2 4 0_4;down
P1 1 0_1;down
W 0_1 0;right
W 0 0_4;right
W 3 4;right
_images/common-base.png

ferrite-choke1.sch

C1 1 0_1; down, dashed, blue
V1 2 1; down, l=v_c
W 2 3; up=0.5, i=i_c
W 3 4; right=1.5
V2 5 4; down=1.4, fixed, l=\frac{v_d}{2}
V3 4 22; down=1.4, fixed, l=\frac{v_d}{2}
W 5 6; right
W 6 7; down
W 7 8; right=2, i={\frac{i_c}{2} + i_d}
W 22 21; right
W 21 20; up
W 20 19; right=2, i={\frac{i_c}{2} - i_d}
TF 8 9 19 18 core; up, l={}
W 9 10; right=2
W 18 17; right=2
W 10 11; up
W 11 12; right
W 17 16; down
W 16 15; right
R1 12 13; down
R2 13 15; down
# Hack
O 4 13; right
O 6 11; right
W 13 14; right=1.5
W 14 23; down, i=i_c
C2 23 0_23; down, dashed, blue
W 0_1 0_23; right
W 0 0_1; right=0.25
W 0_23 0_24; right=0.25
; draw_nodes=connections, label_nodes=false
_images/ferrite-choke1.png

filter1.sch

P1 1 0; down=1.5
R1 1 2; right
C1 2 3; right
W 0 5; right
C2 3 5; down
W 3 3a; right=0.75
W 5 5a; right=0.75
R2 3a 5a; down
W 3a 3b; right=0.75
W 5a 5b; right=0.75
P2 3b 5b; down
; draw_nodes=connections, label_nodes=none
_images/filter1.png

filter2.sch

P1 1 0; down=1.5
R1 1 2; right
C1 2 3; right
R2 0 4; right
C2 4 5; right
C3 3 5; down
W 3 3a; right=0.75
W 5 5a; right=0.75
R3 3a 5a; down
W 3a 3b; right=0.75
W 5a 5b; right=0.75
P2 3b 5b; down
; draw_nodes=connections, label_nodes=none
_images/filter2.png

fit3.sch

U1 chip3333; right, l={MCU}, pinlabels={vss,vdd}
R1 1 1a; down
V_DD 1a 0; down
L1 1 2; right=1
L2 0 0_2; right
W 2 5; right=0.5
W 0_2 0_5; right=0.5
Cbulk 5 0_5; down=2, kind=electrolytic
L3 5 6; right
L4 0_5 0_6; right
W 6 3; right=0.5
W 0_6 0_3; right=0.5
L5 3 4; right, color=blue
L6 0_3 0_4; right, color=blue
W 4 U1.vdd; down=0.25, color=blue
W 0_4 U1.vss; up=0.25, color=blue
Clocal 6 0_6; down, color=blue
A U1.tl
A U1.br
;;\node[blue,draw,dashed,inner sep=8mm, fit=(Cbulk) (U1@tl) (U1@br), label=PCB]{};
; label_nodes=none, draw_nodes=connections, label_values=false, label_ids=false
_images/fit3.png

non-ideal-transformer-primary.sch

R1 1 2; right
L1 2 3 {L_1 - a * M}; right
L3 4 0_4 {a * M}; down
P1 1 0; down, v_=v_1
W 0 0_3; right
W 3 4; right=0.5
W 0_3 0_4; right=0.5
W 4 5; right=0.5
W 0_4 0_7; right=0.5
L2 5 6 {a**2 * L_2 - a * M}; right
R2 6 7 {a**2 * R_2}; right
W 7 10; right=0.5
TF 8 0_8 10 0_7; right, l={N_1:N_2}
W 8 9; right
W 0_8 0_9; right
P2 9 0_9; down, v^=v_2
;label_nodes=False, draw_nodes=connections, label_ids=False
_images/non-ideal-transformer-primary.png

non-ideal-transformer.sch

R1 1 2; right
L1 2 3 {L_1 - a * M}; right
L3 3 0_3 {a * M}; down=1.5
P1 1 0; down, v_=v_1
W 0 0_3; right
W 3 4; right
W 0_3 0_4; right
TF 5 0_5 4 0_4; right, l={N_1:N_2}
W 5 6; right=0.5
W 0_5 0_6; right=0.5
L2 6 7 {L_2 - M / a}; right
R2 7 8; right
P2 8 0_8; down, v^=v_2
W 0_6 0_8; right
;label_nodes=False, draw_nodes=connections, label_ids=False
_images/non-ideal-transformer.png

Block diagrams¶

LTFT.sch

S1 box; right=1.9, aspect=2.1, draw=white, l={Transfer function\\$H(s)$}
S2 box; right=1.9, aspect=2.1, draw=white, l={Impulse response\\$h(t)$}
S3 box; right=1.9, aspect=2.1, draw=white, l={Frequency response\\$H(\mathrm{j}2\pi f)$ or $H(f)$}
S4 box; right, l={$\mathcal{L}^{-1}\left\{.\right\}$}
S5 box; right, l={$\mathcal{F}\left\{.\right\}$}
S6 box; right, l={$s=\mathrm{j}2\pi f$}
W S1.e S4.w; right=0.4, startarrow=tri, endarrow=tri, color=blue
W S4.e S2.w; right=0.4, startarrow=tri, endarrow=tri, color=black!70!green
W S2.s 4; down, color=black!70!green
W 4 S5.e; left=0.4, endarrow=tri, color=black!70!green
W S5.w S3.e; left=0.4, startarrow=tri, endarrow=tri, color=purple
W S1.s S6.n; down=0.4, endarrow=tri, color=blue
W S6.s S3.n; down=0.4, endarrow=tri, color=purple
O S4.mid S5.mid; down=1.3
; label_nodes=alpha, draw_nodes=none, label_ids=false
_images/LTFT.png

domains.sch

S1 box; right=1.9, aspect=2.1, draw=white, l={Laplace domain\\$H(s)$}
S2 box; right=1.9, aspect=2.1, draw=white, l={Time domain\\$h(t)$}
S3 box; right=1.9, aspect=2.1, draw=white, l={Angular frequency response domain\\$H(\mathrm{j}\omega)$}
S4 box; right, l={$\mathcal{L}\left\{.\right\}$}
S5 box; right=1.9, aspect=2.1, draw=white, l={Angular Fourier domain\\$H(\omega)$}
S6 box; right, l={$s=\mathrm{j}\omega$}
S7 box; right, l={$\mathcal{F}_{\omega}\left\{.\right\}$}
S8 box; right=1.9, aspect=2.1, draw=white, l={Equivalent if causal and poles in LHS}
S9 box; right, l={$\mathcal{F}\left\{.\right\}$}
S10 box; right=1.9, aspect=2.1, draw=white, l={Fourier domain\\$H(f)$}
S11 box; right, l={$f=\frac{\omega}{2\pi}$}

W S1.e S4.w; right=0.4, startarrow=tri, color=blue
W S4.e S2.w; right=0.4, startarrow=tri, color=black!70!green
W S2.s S7.n; down=0.4, endarrow=tri, color=black!70!green
W S7.s S5.n; down=0.4, endarrow=tri, color=green
W S1.s S6.n; down=0.4, endarrow=tri, color=blue
W S6.s S3.n; down=0.4, endarrow=tri, color=purple
W S3.e S8.w; right=0.4, dashed, color=purple
W S8.e S5.w; right=0.4, dashed, color=green

W S2.e S9.w; right=0.4, endarrow=tri, color=black!70!green
W S9.e S10.w; right=0.4, endarrow=tri, color=magenta
W S10.s S11.n; down=0.4, endarrow=tri, color=magenta
W S11.s 5; down=0.4, color=green
W 5 S5.e; left, endarrow=tri, color=green

; label_nodes=alpha, draw_nodes=none, label_ids=false
_images/domains.png

fir5.sch

W x 1; right
W 1 S1.w; right=0.5, endarrow=tri
S1 box; right=0.5, l=$z^{-1}$
S2 circle; right=0.5, l=$\times$
S3 circle; right=0.5, l=$\times$
S4 circle; right=0.5, l=$+$
W S1.e 2; right=0.5
W 3 S4.w; right=1.25, endarrow=tri
W 1 S2.n; down
W S2.s 3; down
W a0 S2.w; right=0.5, endarrow=tri
W 2 S3.n; down, endarrow=tri
W S3.s S4.n; down, endarrow=tri
W a1 S3.w; right=0.5, endarrow=tri
W S4.e y; right=0.5, endarrow=tri
# Align multipliers
O S2.w S3.w; right
; draw_nodes=false, label_nodes=alpha
_images/fir5.png

negative-feedback2.sch

W 1 SP1._1; right=0.5, endarrow=tri, l=V_{in}
SP1 pm ._1 ._2 ._3; right=1, l={}
W SP1._3 S1.w; endarrow=tri, l=V_d
S1 box; right=1.5, aspect=1.5, l=Open-loop gain (A)
W S1.e 2; right, l=V_{out}
W 2 3; down
S2 box; right=1.5, aspect=1.5, l=Attenuator $\beta$
W 3 S2.e; left, endarrow=tri
W S2.w 4; left
W 4 SP1._2; up, endarrow=tri
W 2 5; right=0.5, endarrow=tri
; draw_nodes=false, label_nodes=false
_images/negative-feedback2.png

transforms.sch

S1 box; right=1.9, aspect=2.1, draw=white, l={Laplace domain\\$H(s)$}
S2 box; right=1.9, aspect=2.1, draw=white, l={Time domain\\$h(t)$}
S3 box; right=1.9, aspect=2.1, draw=white, l={Angular frequency response domain\\$H(\mathrm{j}\omega)$}
S4 box; right, l={$\mathcal{L}^{-1}\left\{.\right\}$}
S5 box; right=1.9, aspect=2.1, draw=white, l={Angular Fourier domain\\$H(\omega)$}
S6 box; right, l={$s=\mathrm{j}\omega$}
S7 box; right, l={$\mathcal{F}_{\omega}\left\{.\right\}$}
S8 box; right=1.9, aspect=2.1, draw=white, l={Equivalent if causal and poles in LHS}
W S1.e S4.w; right=0.4, startarrow=tri, endarrow=tri, color=blue
W S4.e S2.w; right=0.4, startarrow=tri, endarrow=tri, color=black!70!green
W S2.s S7.n; down=0.4, startarrow=tri, endarrow=tri, color=black!70!green
W S7.s S5.n; down=0.4, startarrow=tri, endarrow=tri, color=green
W S1.s S6.n; down=0.4, startarrow=tri, endarrow=tri, color=blue
W S6.s S3.n; down=0.4, startarrow=tri, endarrow=tri, color=purple
W S3.e S8.w; right=0.4, dashed, color=purple
W S8.e S5.w; right=0.4, dashed, color=green
; label_nodes=alpha, draw_nodes=none, label_ids=false
_images/transforms.png

Two port networks¶

TPA.sch

P 1 2; down, v_=V_1
W 1 9; right=0.75, i=I_1
W 2 10; right=0.75, i<=I_1
I1a 10 9; up
V1a 9 5; right
W 10 6; right
TPA 7 8 5 6; right, l={Source-free A-parameters two-port}
W 7 3; right=0.5, i=I_2
W 8 4; right=0.5, i<=I_2
P 3 4; down, v^=V_2
; label_nodes=none, draw_nodes=connections
_images/TPA.png

TPB.sch

P 1 2; down, v_=V_1
W 1 5; right=0.5, i=I_1
W 2 6; right=0.5, i<=I_1
TPB 7 8 5 6; right, l={Source-free B-parameters two-port}
V2b 9 7; left
W 8 10; right
I2b 10 9; up
W 9 3; right=0.5, i=I_2
W 10 4; right=0.5, i<=I_2
P 3 4; down, v^=V_2
; label_nodes=none, draw_nodes=connections
_images/TPB.png

TPG.sch

P 1 2; down, v_=V_1
W 1 11; right=0.75, i=I_1
W 2 12; right=0.75, i<=I_1
I1g 12 11; up
W 11 5; right=0.25
W 12 6; right=0.25
TPG 7 8 5 6; right, l={Source-free G-parameters two-port}
V2g 9 7; left
W 8 10; right
W 9 3; right=0.5, i=I_2
W 10 4; right=0.5, i<=I_2
P 3 4; down, v^=V_2
; label_nodes=none, draw_nodes=connections
_images/TPG.png

TPH.sch

P 1 2; down, v_=V_1
W 1 11; right=0.5, i=I_1
W 2 12; right=0.5, i<=I_1
V1h 11 5; right
W 12 6; right
TPH 7 8 5 6; right, l={Source-free H-parameters two-port}
W 7 9; right=0.25
W 8 10; right=0.25
I2h 10 9; up
W 9 3; right=0.5, i=I_2
W 10 4; right=0.5, i<=I_2
P 3 4; down, v^=V_2
; label_nodes=none, draw_nodes=connections
_images/TPH.png

TPY.sch

P 1 2; down, v_=V_1
W 1 11; right=0.75, i=I_1
W 2 12; right=0.75, i<=I_1
I1y 12 11; up
W 11 5; right=0.25
W 12 6; right=0.25
TPY 7 8 5 6; right, l={Source-free Y-parameters two-port}
W 7 9; right=0.25
W 8 10; right=0.25
I2y 10 9; up
W 9 3; right=0.5, i=I_2
W 10 4; right=0.5, i<=I_2
P 3 4; down, v^=V_2
; label_nodes=none, draw_nodes=connections
_images/TPY.png

TPZ.sch

P 1 2; down, v_=V_1
W 1 11; right=0.25, i=I_1
W 2 12; right=0.25, i<=I_1
V1z 11 5; right
W 12 6; right
TPZ 7 8 5 6; right, l={Source-free Z-parameters two-port}
V2z 9 7; left
W 8 10; right
W 9 3; right=0.25, i=I_2
W 10 4; right=0.25, i<=I_2
P 3 4; down, v^=V_2
; label_nodes=none, draw_nodes=connections
_images/TPZ.png

series.sch

P1 1 0; down, v_=V_1
W 1 2; right=0.5, i=I_1
W 0 0_2; right=0.5
Z 2 4; right, l=OP
W 3 4; left=0.5, i=I_2
W 0_2 0_3; right=0.5
P2 3 0_3; down, v^=V_2
;label_nodes=False, draw_nodes=connections
_images/series.png

shunt.sch

P1 1 0; down, v_=V_1
W 1 2; right, i=I_1
W 0 0_2; right
Z 2 0_2; down, l=OP
W 3 2; left, i=I_2
W 0_2 0_3; right
P2 3 0_3; down, v^=V_2
;label_nodes=False, draw_nodes=connections
_images/shunt.png

pisection.sch

P1 1 0; down, v_=V_1
W 1 1_1; right=0.75, i=I_1
W 0 0_1; right=0.5
Y1 1_1 0_1 Y; down, l=OP1
W 0_1 0_3; right=0.5
Z 1_1 2_1 Z; right=1.5, l=OP2
Y2 2_1 0_3 Y; down, l=OP3
W 2 2_1; left=0.75, i=I_2
W 0_3 0_2; right=0.5
P2 2 0_2; down, v^=V_2
;label_nodes=False, draw_nodes=connections
_images/pisection.png

tsection.sch

P1 1 0; down, v_=V_1
W 1 1_1; right=0.5, i=I_1
W 0 0_1; right=0.5
W 0_1 0_3; right=0.5
Z1 1_1 2_1 Z; right, l=OP1
Y 2_1 0_3 Y; down, l=OP2
Z2 2_1 4_1; right, l=OP3
W 2 4_1; left=0.5, i=I_2
W 0_3 0_2; right=0.5
P2 2 0_2; down, v^=V_2
;label_nodes=False, draw_nodes=connections
_images/tsection.png

Components¶

ADC1.sch

U1 adc; right, pinnames=all, pinnodes=all, l={ADC}
_images/ADC1.png

arrows.sch

W 1 2; right, endarrow=tri
W 2 3; right, endarrow=otri
W 3 4; right, startarrow=open triangle 90, endarrow=open triangle 90
W 4 5; right, startarrow=stealth, endarrow=stealth
; help_lines=1, draw_nodes=none
_images/arrows.png

antennas.sch

ANT1 1; left, kind=tx, mirror, l=tx
ANT2 1; right, kind=rx, l=rx
_images/antennas.png

batteries.sch

BAT1 1 2; right, l=default
BAT2 2 3; right, kind=cell1, l=cell1
; label_nodes=false, draw_nodes=connections
_images/batteries.png

buffers.sch

U1 buffer; right
U2 inverter; right
W U1.out U2.in; right=0.5
_images/buffers.png

cable-coax.sch

Cable1; right=2, dashed, kind=coax
W 1 Cable1.in; right=0.5
W Cable1.out 2; right=0.5
_images/cable-coax.png

cable-tp.sch

Cable1; right=2, dashed, kind=shieldedtwistedpair
W 1+ Cable1.in+; right=0.5
W 1- Cable1.in-; right=0.5
W Cable1.out+ 2+; right=0.5
W Cable1.out- 2-; right=0.5
_images/cable-tp.png

cable-twinax.sch

Cable1; right=2, dashed, kind=twinax
W 1+ Cable1.in+; right=0.5
W 1- Cable1.in-; right=0.5
W Cable1.out+ 2+; right=0.5
W Cable1.out- 2-; right=0.5
_images/cable-twinax.png

cable-utp.sch

Cable1; right=2, dashed, kind=twistedpair
W 1+ Cable1.in+; right=0.5
W 1- Cable1.in-; right=0.5
W Cable1.out+ 2+; right=0.5
W Cable1.out- 2-; right=0.5
_images/cable-utp.png

capacitors.sch

C1 1 2; right, l=
C2 2 3; right, kind=electrolytic, l=electrolytic
C3 3 4; right, kind=polar, l=polar
C4 4 5; right, kind=variable, l=variable
C5 5 6; right, kind=curved, l=curved
C6 6 7; right, kind=sensor, l=sensor
C7 7 8; right, kind=tunable, l=tunable
; label_nodes=false, draw_nodes=connections
_images/capacitors.png

connections1.sch

W 1 2; right=0.2, input, l=input, fill=blue!50
W 3 4; right=0.2, output, l=output
W 5 6; right=0.2, bidir, l=bidir
W 7 8; right=0.2, pad, l=pad
O 1 3; right
O 3 5; right
O 5 7; right
; draw_nodes=connections, label_nodes=none
_images/connections1.png

connections2.sch

W 1 2; right=0.2, input, l=PA0, fill=blue!50
W 3 4; right=0.2, input=1.25, l=PA0
W 5 6; right=0.2, input=1.25, l=PA0, aspect=1.25
W 7 8; right=0.2, input, l=PA0, aspect=0.8
O 1 3; right=1.5
O 3 5; right=1.5
O 5 7; right=1.5
_images/connections2.png

CPE1.sch

CPE1 1 0; right
_images/CPE1.png

DAC3.sch

U1 dac; right, pinnames=all, pinnodes=all, l={DAC}
_images/DAC3.png

diodes.sch

D1 1 2; right, l=diode
D2 2 3; right, kind=schottky, l=schottky
D3 3 4; right, kind=led, l=led
D4 4 5; right, kind=zener, l=zener
D5 5 6; right, kind=zzener, l=zzener
D6 6 7; right, kind=tunnel, l=tunnel
D7 7 8; right, kind=photo, l=photo
D8 8 9; right, kind=varcap, l=varcap
D9 9 10; right, kind=bidirectional, l=bidirectional
D10 10 11; right, kind=tvs, l=tvs
D11 11 12; right, kind=laser, l=laser
; draw_nodes=none, label_nodes=none
_images/diodes.png

diodes2.sch

D1 1 2; right, l=empty
D2 2 3; right, style=full, l=full
D3 3 4; right, style=stroke, l=stroke
; draw_nodes=none, label_nodes=none
_images/diodes2.png

FB1.sch

FB1 1 2; right
_images/FB1.png

fdopamps.sch

E1 out+1 out-1 fdopamp in+1 in-1 ocm1 A; right=1, pinnodes=all, pinnames=all
E2 out+2 out-2 fdopamp in+2 in-2 ocm2 A; right=1, mirror, pinnodes=all, pinnames=all
O in+1 in-2; right=3
; label_nodes=none
_images/fdopamps.png

flipflops.sch

U1 dff; right, pinnames=all, pinlabels=all, pinnodes=all, l={dff}
U2 jkff; right, pinnames=all, pinlabels=all, pinnodes=all, l={jkff}
U3 rslatch; right, pinnames=all, pinlabels=all, pinnodes=all, l={rslatch}
U4 chip3131; right, pinlabels={l1=D,l2=>,r1=Q,r3=Q$\slash$}, pinnodes=all, l={dff}
O U1.mid U2.mid; right=2
O U2.mid U3.mid; right=2
O U3.mid U4.mid; right=3
_images/flipflops.png

grounds.sch

# signal ground
W 1 01; down=0.2, sground
A 1; l=sground, anchor=s
W 1 2; right
# earth ground
W 2 02; down=0.2, ground
A 2; l=ground, anchor=s
W 2 3; right
# chassis ground
W 3 03; down=0.2, cground
A 3; l=cground, anchor=s
W 3 4; right
# noiseless ground
W 4 04; down=0.2, nground
A 4; l=nground, anchor=s
W 4 5; right
# protected ground
W 5 05; down=0.2, pground
A 5; l=pground, anchor=s
W 5 6; right
# reference ground
W 6 06; down=0.2, rground
A 6; l=rground, anchor=s
W 6 7; right
# 0V
W 7 07; down=0.2, 0V
A 7; l=0V, anchor=s
; label_nodes=none
_images/grounds.png

GY1.sch

GY1 1 2 3 4 R; right
_images/GY1.png

hsources.sch

V1 1 2; down
I1 3 4; down
O 1 3; right
O 2 4; right

V5 5 6; up
I5 7 8; up
O 5 7; right
O 6 8; right

O 3 6; right
_images/hsources.png

massspringdamper1.sch

k 1 2; right
r 2 3; right
m 3 0; right
_images/massspringdamper1.png

meters1.sch

V 1 0; down
AM 1 2; right=1.5
R 2 3; down
W 0 3; right
W 2 2_1; right
W 3 3_1; right
VM 2_1 3_1; down
_images/meters1.png

misc.sch

MISC1 1 2; right, kind=thermistor, l=thermistor
MISC2 2 3; right, kind=memristor, l=memristor
_images/misc.png

multiplexers.sch

U1 mux21; right=1.5, pinnodes=all, pinnames=all, l=mux21
U2 mux42; right=1.5, pinnodes=all, pinnames=all, l=mux42
O U1.mid U2.mid; right=2
_images/multiplexers.png

opamps.sch

E1 out1 0 opamp in+1 in-1 A; right=1, pinnodes=all, pinnames=all
E2 out2 0 opamp in+2 in-2 A; right=1, mirror, pinnodes=all, pinnames=all
O out1 out2; right=3
; label_nodes=none
_images/opamps.png

resistors1.sch

R1 1 2; right
R2 2 3; right=2
R3 3 4; right=3
;help_lines=1
_images/resistors1.png

resistors2.sch

R1 1 2; right
R2 2 3; right=2
R3 3 4; right=3
;node_spacing=1.5, help_lines=1
_images/resistors2.png

resistors3.sch

R1 1 2; right
R2 2 3; right=2
R3 3 4; right=3
;cpt_size=1, help_lines=1
_images/resistors3.png

resistors4.sch

R1 1 2; right
R2 2 3; right=2
R3 3 4; right=3
;cpt_size=1, node_spacing=1, help_lines=1
_images/resistors4.png

resistors5.sch

R1 1 2; right
R2 2 3; right=2
R3 3 4; right=3
;scale=0.5, help_lines=1
_images/resistors5.png

resistors6.sch

R1 1 2; right
R2 2 3; right=2, scale=2
R3 3 4; right=3, scale=3
;help_lines=1
_images/resistors6.png

resistors7.sch

R1 1 2; right
R2 2 3; right=2
R3 3 4; right=3
;help_lines=1
_images/resistors7.png

switches.sch

SW1 1 2 no; right
SW2 2 3 nc; right
SW3 3 4 push 2; right
SW4 4 5 6 spdt; right
_images/switches.png

switches2.sch

SW1 1 2 no; right
SW2 2 3 no; right, mirror
SW3 3 4 no; right, mirror, invert
SW4 4 5 no; right, invert
_images/switches2.png

transformers.sch

TF1 1 2 3 4; right

TF2 11 12 13 14 core; right

TF3 21 22 23 24 tap _25 _26; right
W 25 _25; right=0.5
W _26 26; right=0.5

O 1 13; right
O 11 23; right
_images/transformers.png

transistors.sch

Q1 1 2 3 npn Q1; up, l=npn
Q2 4 5 3 pnp Q2; up, l=pnp
J1 4 6 7 njf J1; up, l=njf
J2 8 9 7 pjf J2; up, l=pjf
M1 8 10 11 nmos M1; up, l=nmos
M2 12 13 11 pmos M2; up, l=pmos
M3 12 14 15 nmos M3; up, l=nmosd
M4 16 17 15 pmos M4; up, l=pmosd

# Hack to include labels in bounding box
O 7 18; up=0.8

O 1 19; down=1.5

M5 19 20 21  M5; up, kind=nfetd, l=nfetd
M6 22 23 21  M6; up, kind=pfetd, l=pfetd
M7 22 24 25  M7; up, kind=nfet, l=nfet
M8 26 27 25  M8; up, kind=pfet, l=pfet
M9 26 28 29  M9; up, kind=nigfetd, l=nigfetd
M10 30 31 29  M10; up, kind=pigfetd, l=pigfetd
M11 30 32 33  M11; up, kind=nigfete, l=nigfete
M12 34 35 33  M12; up, kind=pigfete, l=pigfete
M13 34 36 37  M13; up, kind=nigfetebulk, l=nigfetebulk
M14 38 39 37  M14; up, kind=pigfetebulk, l=pigfetebulk

O 19 40; down=1.5

M15 40 41 42  M15; up=1.5, kind=nfet, l=nfet/bodydiode, bodydiode
M16 43 44 42  M16; up=1.5, kind=pfet, l=pfet/bodydiode, bodydiode
M17 43 45 46  M17; up=1.5, kind=nmosd, l=nmosd/bulk, bulk
M18 47 48 46  M18; up=1.5, kind=pmosd, l=pmosd/bulk, bulk

; label_nodes=none, draw_nodes=connections
_images/transistors.png

transistors2.sch

Q1 0 1 2; right
Q2 3 4 5; right, mirror
Q3 6 7 8; right, invert
Q4 9 10 11; right, mirror, invert

O 0 3; right
O 3 6; right
O 6 9; right
_images/transistors2.png

Uinamp.sch

U1 inamp; right=1.5, pinnodes=all, pinnames=all, l=inamp
; help_lines=1.5
_images/Uinamp.png

Uisoamp.sch

U1 isoamp; right=1.5, pinnodes=all, pinnames=all, l=isoamp
; help_lines=1.5
_images/Uisoamp.png

Ufdopamp.sch

U1 fdopamp; right=1.5, pinnodes=all, pinnames=all, l=fdopamp
; help_lines=1.5
_images/Ufdopamp.png

Uopamp.sch

U1 opamp; right=1.5, pinnodes=all, pinnames=all, l=opamp
; help_lines=1.5
_images/Uopamp.png

variable1.sch

V 1 0 ac; down=1.5
L 1 2; right=1.5, variable
R 2 3; down, variable
W 0 3; right
W 2 2_1; right
W 3 3_1; right
C 2_1 3_1; down, variable
_images/variable1.png

vsources.sch

V1 1 2; right
O 2 3; right
I1 3 4; right

O 4 6; right

V2 5 6; left
O 5 8; right
I2 7 8; left
_images/vsources.png

wirestyles.sch

W 1 2; right
W 2 3; right, dashed
W 3 4; right, dotted
W 4 5; right, thick
W 5 6; right, ultra thick
W 6 7; right, ultra thick, dashed
W 7 8; right, line width=4pt
; help_lines=1
_images/wirestyles.png

XT1.sch

XT1 1 2; right
_images/XT1.png

Chips¶

chips.sch

U1 chip1313; right, pinnames=all, pinnodes=all, l={chip1313}
U2 chip2121; right, pinnames=all, pinnodes=all, l={chip2121}
U3 chip3131; right, pinnames=all, pinnodes=all, l={chip3131}
U4 chip3333; right, pinnames=all, pinnodes=all, l={chip3333}
U5 chip2222; right, pinnames=all, pinnodes=all, l={chip2222}
U6 chip4141; right, pinnames=all, pinnodes=all, l={chip4141}
O U1.mid U2.mid; right=3
O U2.mid U3.mid; right=3
O U1.mid U4.mid; down=3
O U4.mid U5.mid; right=3
O U5.mid U6.mid; right=3
_images/chips.png

chips2.sch

U1 chip1313; right, aspect=1.333, pinnames=all, pinnodes=all, l={chip1313}
U2 chip2121; right, aspect=1.333, pinnames=all, pinnodes=all, l={chip2121}
U3 chip3131; right, aspect=1.333, pinnames=all, pinnodes=all, l={chip3131}
U4 chip3333; right, aspect=1.333, pinnames=all, pinnodes=all, l={chip3333}
U5 chip2222; right, aspect=1.333, pinnames=all, pinnodes=all, l={chip2222}
U6 chip4141; right, aspect=1.333, pinnames=all, pinnodes=all, l={chip4141}
O U1.mid U2.mid; right=3
O U2.mid U3.mid; right=3
O U1.mid U4.mid; down=3
O U4.mid U5.mid; right=3
O U5.mid U6.mid; right=3
_images/chips2.png

chips3.sch

U1 chip1313; right=1.5, pinnames=all, pinnodes=all, l={chip1313}
U2 chip2121; right=1.5, pinnames=all, pinnodes=all, l={chip2121}
U3 chip3131; right=1.5, pinnames=all, pinnodes=all, l={chip3131}
U4 chip3333; right=1.5, pinnames=all, pinnodes=all, l={chip3333}
U5 chip2222; right=1.5, pinnames=all, pinnodes=all, l={chip2222}
U6 chip4141; right=1.5, pinnames=all, pinnodes=all, l={chip4141}
O U1.mid U2.mid; right=3
O U2.mid U3.mid; right=3
O U1.mid U4.mid; down=3
O U4.mid U5.mid; right=3
O U5.mid U6.mid; right=3
_images/chips3.png

Shapes¶

Striangle2.sch

S1 triangle; right=2, aspect=0.75, pinnodes=all, pinnames=all, l={triangle}
; help_lines=1
_images/Striangle2.png

Sbox1.sch

S1 box; right=1.5, pinnodes=all, pinnames=all, l={}
; help_lines=1
_images/Sbox1.png

Scircle2.sch

S1 circle; right=2, pinnodes=all, pinnames=all, l={circle}
; help_lines=1
_images/Scircle2.png

circles.sch

S1 circle; right, fill opacity=0.5, fill=blue
S2 circle; right, fill opacity=0.5, fill=green
S3 circle; right, fill opacity=0.5, fill=red
O S1.mid S2.mid; size=0.7, rotate=0
O S1.mid S3.mid; size=0.7, rotate=-60
_images/circles.png

Labels¶

annotate1.sch

R 1 2; right
A1 1; l=hello, anchor=north
A2 2; l=world, anchor=west
; label_nodes=false
_images/annotate1.png

current_labels1.sch

R1 1 2; right=1.5, i=I, l=
R2 2 3; right=1.5, i>^=I, l=$>\wedge$
R3 3 4; right=1.5, i>_=I, l=$>\_$
R4 4 5; right=1.5, i^>=I, l=$\wedge>$
R5 5 6; right=1.5, i_>=I, l=$\_>$
R6 6 7; right=1.5, i<^=-I, l=$<\wedge$
R7 7 8; right=1.5, i<_=-I, l=$<\_$
R8 8 9; right=1.5, i^<=-I, l=$\wedge<$
R9 9 10; right=1.5, i_<=-I, l=$\_<$
; label_nodes=none, draw_nodes=none
_images/current_labels1.png

current_labels2.sch

R1 2 1; left=1.5, i=I, l=
R2 3 2; left=1.5, i>^=I, l=$>\wedge$
R3 4 3; left=1.5, i>_=I, l=$>\_$
R4 5 4; left=1.5, i^>=I, l=$\wedge>$
R5 6 5; left=1.5, i_>=I, l=$\_>$
R6 7 6; left=1.5, i<^=-I, l=$<\wedge$
R7 8 7; left=1.5, i<_=-I, l=$<\_$
R8 9 8; left=1.5, i^<=-I, l=$\wedge<$
R9 10 9; left=1.5, i_<=-I, l=$\_<$
; label_nodes=none, draw_nodes=none
_images/current_labels2.png

flow_labels1.sch

R1 1 2; right=1.5, f=I, l=
R2 2 3; right=1.5, f>^=I, l=$>\wedge$
R3 3 4; right=1.5, f>_=I, l=$>\_$
R4 4 5; right=1.5, f^>=I, l=$\wedge>$
R5 5 6; right=1.5, f_>=I, l=$\_>$
R6 6 7; right=1.5, f<^=-I, l=$<\wedge$
R7 7 8; right=1.5, f<_=-I, l=$<\_$
R8 8 9; right=1.5, f^<=-I, l=$\wedge<$
R9 9 10; right=1.5, f_<=-I, l=$\_<$
; label_nodes=none, draw_nodes=none
_images/flow_labels1.png

labels1.sch

R1 1 2; right=1.5, l=A
R2 2 3; right=1.5, l_=B
R3 3 4; right=1.5, l^=C
; label_nodes=none, draw_nodes=none
_images/labels1.png

voltage_labels1.sch

R1 1 2; right=1.5, v=V_1, l=
R2 2 3; right=1.5, v^=V_2, l=
R3 3 4; right=1.5, v_=V_3, l=
; label_nodes=none, draw_nodes=none
_images/voltage_labels1.png

Rlabels.sch

R1 1 2;
R2 2 3; a={1\,k}
R3 3 4; a_={1\,k}, l^=R_2
; label_nodes=none, draw_nodes=none, node_spacing=3
_images/Rlabels.png

Digital circuits¶

PIO1.sch

U1 buffer; right, l={}, fill=blue!50
U2 buffer; right, fliplr, l={}, fill=red!50
W U2.in 1; right=0.5
W 1 3; down=0.5
W 3 pin; bidir, l=PA0, fill=purple!50
W 2 3; up=0.5
W U1.out 2; right=0.5
W 2i U1.in; right=0.5
W 1o U2.out; right=0.5
W U1.vss 4; down=0.5
; label_nodes=none, draw_nodes=connections
_images/PIO1.png

PIO-input2.sch

U1 dff; right=1, fliplr, pinlabels={q,d,clk}, l={}, fill=red!50
U2 buffer; right, fliplr, l={}, fill=red!50
W U2.out U1.d; left=0.5
W U2.in 3; right=0.5, bidir, l=PA0, fill=purple!50
W U1.clk 4; right=0.5
W 4 5; down=0.5, input
A 5; l={PIO clock}, anchor=south west
; label_nodes=none, draw_nodes=connections
_images/PIO-input2.png

PIO-input3.sch

U3 dff; right=1, fliplr, pinlabels={q,d,clk}, l={}, fill=red!50
W U3.d U1.q; right=0.5
U1 dff; right=1, fliplr, pinlabels={q,d,clk}, l={}, fill=red!50
U2 buffer; right, fliplr, l={}, fill=red!50
W U2.out U1.d; left=0.5
W U2.in 3; right=0.5, bidir, l=PA0, fill=purple!50
W U1.clk 4; right=0.5
W 4 5; down=0.75
W U3.clk 6; right=0.25
W 6 7; down=0.75
W 7 5; right=1.5
W 5 8; right=0.5
A 8; l={PIO clock}, anchor=south west
; label_nodes=none, draw_nodes=connections
_images/PIO-input3.png

PIO-output2.sch

U1 dff; right=1, pinlabels={q,d,clk}, l={PORT}, fill=blue!50
U2 buffer; right, l={}, fill=blue!50
W U1.q U2.in; right=0.5
W U2.out 3; right=0.5, bidir, l=PA0, fill=purple!50

O U1.q U3.q; down=1.5
U3 dff; right=1, pinlabels={q,d,clk}, l={DD}, fill=purple!50
W U3.q U2.vss; steps=-|, free
; label_nodes=none, draw_nodes=connections
_images/PIO-output2.png

PIO-pullup2.sch

W 3 3a; up=0.1, rground, l=VDDIO
M1 1 2 3 pmos; right, l={}
R 1 4; down, l={}
W 4 5; right=0.5, bidir, l=PA0, fill=purple!50
U2 buffer; right, fliplr, l={}, fill=red!50
W U2.in 4; right=1
U1 dff; right=1, pinlabels={q,d,clk}, fill=green!50, l={}
W U1.q 2; right=0.01
; label_nodes=none, draw_nodes=connections
_images/PIO-pullup2.png

mcu-bt.sch

U1 chip3131; right=1.8, l=MCU, pinlabels={r3=RXD, r2=TXD, r1=PIO1}, aspect=0.8
U2 chip3131; right=1.8, l={\hspace{5mm}Bluetooth}, pinlabels={l2=RXD, l3=TXD}, aspect=0.8
W U1.r2 U2.l2; right=2.5
W U1.r3 U2.l3; right=2.5
U3 regulator; right=1.5, aspect=1.5, pinlabels={en=EN}, l=VREG
W U1.r1 1; right=0.25
W 1 U3.en; up
W U3.out 2; right=0.5
W 2 U2.vdd; down
U4 regulator; right=1.5, aspect=1.5, l=VREG
W U4.out 3; right=0.5
W 3 U1.vdd; down
# Hack
O 3 U3.in; right
W 5 U4.in; right=0.5
W 5 _5; up=0.4, implicit, l=V_{bat}
W 6 U3.in; right=0.5
W 6 _6; up=0.4, implicit, l=V_{bat}
W U1.vss 0_5; down=0.1, 0V
W U2.vss 0_6; down=0.1, 0V
W U4.gnd 0_7; down=0.1, 0V
W U3.gnd 0_8; down=0.1, 0V
R 1 7; right
W 7 0_9; down=0.1, 0V
; draw_nodes=connections, label_nodes=none, node_spacing=2
_images/mcu-bt.png

cmos-backdrive1.sch

U1 inverter; right
U2 inverter; right
W U1.out U2.in; right=1
W U1.vss 4_2; down=0.3, 0V
W U2.vss 4_3; down=0.3, 0V
W U1.vdd 3_2; up=0.3, implicit, l=V_{DD1}
W U2.vdd 3_3; up=0.3, implicit, l=V_{DD2}
#; help_lines=0.05
;draw_nodes=connections,label_nodes=false,thickness=2
_images/cmos-backdrive1.png

cmos-backdrive2.sch

U1 inverter; right=2, l={}
U2 inverter; right=2, l={}
W U1.out U2.in; right=1, color=red
W U1.vss 4_2; down=0.3, 0V
W U2.vss 4_3; down=0.3, 0V
W U1.vdd 3_2; up=0.3, implicit, l=V_{DD1}, color=red
W U2.vdd 3_3; up=0.3, implicit, l=V_{DD2}, color=red
W U2.in 7_1; right=0.25, dashed, fixed, color=red
D1 7_1 6_1; up=0.25, scale=0.5, l=, color=red
D2 6_2 7_1; up=0.25, scale=0.5, l=
W 6_1 U2.vdd; right=0.6, dashed, color=red
W 6_2 U2.vss; right=0.6, dashed
M1 1 2 3 pmos; right=0.4, scale=0.4, l={}, color=red
M2 1 4 5 nmos; right=0.4, scale=0.4, l={}
W 3 3_1; up=0.0, color=red
W 3_1 U1.vdd; right=0.2, dashed, color=red
W 5 5_1; down=0.0
W 5_1 U1.vss; right=0.2, dashed
W 1 U1.out; right, dashed, color=red
;draw_nodes=connections,label_nodes=false,thickness=2
_images/cmos-backdrive2.png

I2C2.sch

U1 chip2222; right, pindefs={sda=b1,scl=b2}, pinlabels={sda=SDA,scl=SCL}, l={Master A}
W U1.sda 11; down
W U1.scl 12; down=0.5
U2 chip2222; right, pindefs={sda=b1,scl=b2}, pinlabels={sda=SDA,scl=SCL}, l={Master B}
W U2.sda 61; down
W U2.scl 62; down=0.5
U3 chip2222; right, pindefs={sda=b1,scl=b2}, pinlabels={sda=SDA,scl=SCL}, l={Slave}
W U3.sda 21; down
W U3.scl 22; down=0.5
W 11 61; right=2.5
W 12 62; right=2.5
W 61 21; right=2.5
W 62 22; right=2.5
W 21 31; right=2
W 22 32; right=1.75
W 31 31a; up=0.5
R1 31a 41; up=1.5
R2 32 42; up=1.5
#O 41 42; right
W 41 51; up=0.2, l={VDD}, implicit
W 42 52; up=0.2, l={VDD}, implicit
; draw_nodes=connections, label_nodes=none
_images/I2C2.png

ic1.sch

; draw_nodes=connections, help_lines=1
U1 chip2121; right=2, l={MCU}, pinlabels={r1=PIO1,r2=PIO2}
W U1.vdd VDD; up=0.2, implicit, l=3V3
W U1.vss 0; down=0.7, 0V
R1 U1.r2 1; right
D1 1 3 led; down
W 3 0; down=0.1, 0V
R2 U1.r1 2; right
W 2 5; right
D2 5 4 led; down
W 4 0; down=0.1, 0V
_images/ic1.png

stepup.sch

U1 chip2121; right, l=MCU, pinlabels={r2=PWM2, r1=PWM1}
M1 9 10 11; right
M2 12 13 14; right
W U1.r1 10; right=0.1
W U1.r2 13; right=0.1
TF1 1 2 3 4 tapcore 5 _6; right, l=1:100
W 9 8; up=0.1
W 8 3; right
W 7 5; right=0.5
W 12 4; up=0.1
W 14 14_1; down=0.1, 0V
W 11 11_1; down=1.1, 0V
W 7 7_1; up=0.8, implicit, l=3.9V
W U1.vss _16; down=0.4, 0V
W U1.vdd _17; up=0.2, implicit, l=3.3V
W 1 1_1; right=0.5
W 2 2_1; right=0.5
; draw_nodes=connections, label_nodes=none
_images/stepup.png

Transistor circuits¶

nmosfet_simple_amplifier.sch

W 1 VDD; up=0.05, implicit, l=V_{DD}
Rd 1 3a; down, f={I_{ds} + I_{o}}
W 3a 3; down=0.5
M1 3 4 5; right, kind=nfet
W 3 o; right, f=I_o
P o 7; down, v=V_o
W 7 0; down=0.05, implicit, l=0V
Rs 5 5a; down, f=I_{ds}
W 5a VSS; down=0.05, implicit, l=0V
Rl o 9; right
W 9 6; right=0.5
Vl 6 8; down
W 8 0; down=0.05, implicit, l=0V
W 11 4; right=0.5
P 11 13; down, v=V_{i}
W 13 0; down=0.05, implicit, l=0V
; draw_nodes=connections, label_nodes=none, bipole voltage style={color=blue}, bipole flow style={color=blue}
_images/nmosfet_simple_amplifier.png

mosfet_push_pull_load.sch

W 1a VDD; up=0.05, implicit, l=V_{DD}
W 1a 1; down=0.5, f={I_{dn}}
M1 1 2 3a; right, kind=nfet
M2 5 4 3b; right, kind=pfet
W 3a 3; down=0.5
W 3 3b; down=0.5
W 3 o; right, f=I_o
P o 7; down, v=V_o
W 7 0; down=0.05, implicit, l=0V
W 5 5a; down=0.5, f<=I_{dp}
W 5a VSS; down=0.05, implicit, l=V_{SS}
Rl o 9; right
W 9 6; right=0.5
Vl 6 8; down
W 8 0; down=0.05, implicit, l=0V
W 10 2; right=0.5
W 11 4; right=0.5
P 10 12; down, v=V_{gn}, bipole voltage style={color=blue}
P 11 13; down, v=V_{gp}
W 12 0; down=0.05, implicit, l=0V
W 13 0; down=0.05, implicit, l=0V

; draw_nodes=connections, label_nodes=none, bipole voltage style={color=blue}, bipole flow style={color=blue}
_images/mosfet_push_pull_load.png

BH-mag.sch

VHV 2c 1c; down, color=blue
D1 2c 3; right, color=blue
W 3 3a; right=0.5, color=blue
W 1c 1b; right, color=blue
W 1b 1d; right=0.5, color=blue
C 3a 1d; down, color=blue
W 4 3; down=0.5, color=blue
W 4 4a; right=2, color=blue
MC1 4a 5 6; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QC1, color=blue
W 1b 1; down=0.5, color=blue
W 1 1a; right
MC2 6 7 1a; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QC2
MD1 1a 8 9; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QD1
MD2 9 16 0a; right=1.5, scale=1.5, bodydiode, kind=nfet, l=, color=blue
W 1 1e; down=0.5, color=blue
VLV 1e 0; down, color=blue
W 0 0a; right, color=blue
W 6 6a; right=2, color=blue
W 6a 6b; right=2
MA1 6a 10 12; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QA1, color=blue
MA2 12 11 9a; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QA2
W 9 9a; right=2, color=blue
MB1 6b 14 13a; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QB1
MB2 13a 15 9b; right=1.5, scale=1.5, bodydiode, kind=nfet, l=QB2, color=blue
W 9a 9b; right, color=blue
W 12 12a; right=0.5, color=blue
L 12a 13; right, i>_=i_L, v=v_L, color=blue
W 13 13a; right=0.5, color=blue
# Hack for Circuitikz bounding box problem
O 13a 13b; right=0.8
; draw_nodes=connections, label_nodes=none
_images/BH-mag.png

Opamp circuits¶

opamp-differential-amplifier1.sch

P1 1 0_1; down
P2 4 0_1; down
R1 1 2; right
R2 2_1 3_1; right
E1 3_2 0_3 opamp 2_0 2 A; mirror
W 0_1 0; right
R3 4 2_0; right
R4 2_0 0; down=1.5
W 3_2 3; right
W 0 0_3; right
P3 3 0_3; down
W 2_1 2; down
W 3_1 3_2; down
;draw_nodes=connections
_images/opamp-differential-amplifier1.png

opamp-inverting-amplifier1.sch

E 1 0 opamp 3 2 Ad; right, flipud
R1 4 2; right
R2 2_2 1_1; right
W 2 2_2; up
W 1 1_1; up
W 4 4_2; down=0.5
Vs 4_2 0_3; down
W 0_3 0_1; down=0.5
W 3 0_2; down
W 1 1_2; right
P 1_2 0; down
W 0_1 0_2; right
W 0_2 0; right
; draw_nodes=connections, label_ids=none, label_nodes=primary
_images/opamp-inverting-amplifier1.png

opamp-inverting-integrator.sch

P1 1 0_1; down
R 1 2; right
C 2_1 3_1; right
E1 3_2 0_3 opamp 2_0 2 A; mirror
W 0_1 0; right
W 2_0 0; down
W 3_2 3; right
W 0 0_3; right
P2 3 0_3; down
W 2_1 2; down
W 3_1 3_2; down
_images/opamp-inverting-integrator.png

opamp-transimpedance-amplifier1.sch

E 1 0 opamp 3 2 Ad; right, flipud
W 4 2; right
R 2_2 1_1; right
W 2 2_2; up
W 1 1_1; up
W 4 4_2; down=0.5
Is 4_2 0_3; down
W 0_3 0_1; down=0.5
W 3 0_2; down
W 1 1_2; right
P 1_2 0; down
W 0_1 0_2; right
W 0_2 0; right
; draw_nodes=connections, label_ids=none, label_nodes=primary
_images/opamp-transimpedance-amplifier1.png

opamp-transimpedance-amplifier2.sch

E1 1 0 opamp 0_4 2_1 A; right, mirror
W 1 1_2; right=0.5
P 1_2 0_6; down
Cs 4 0; down
Ca 4_3 0_5; down
W 4_1 4; right
Is 4_1 0_3 ac; down=2
W 0_3 0; right
W 4 4_3; right
Vn 4_3 2 noise; right
W 2 2_1; right=0.5
In 2 0_1 noise; down
W 0_4 0_2; down
W 0 0_5; right
W 0_5 0_1; right
W 0_1 0_2; right
W 0_2 0_6; right=0.5
W 4 4_2; up
VnR 4_2 3 noise; right
R 3 1_1; right
W 1_1 1; down
; draw_nodes=connections
_images/opamp-transimpedance-amplifier2.png

inamp-amplifier1.sch

E 1 2 inamp 3 4 5 6 Ad Ac Rf; right, l=
W 5_1 5; right=0.5
W 6_1 6; right=0.5
Rg 5_1 6_1; down=0.5, scale=0.5
W 2 0; down=0.1, 0V
Vs1 3_2 0_3; down
W 0_3 0; down=0.1, 0V
W 3_2 3; right
Vs2 4 0_4; down
W 0_4 0; down=0.1, 0V
; draw_nodes=connected
_images/inamp-amplifier1.png

fdopamp-amplifier1.sch

Vsp 1 0_1 ; down
W 0_1 0; down=0.1, 0V
W 1 1_1; right
R1 1_1 6; right
Vsm 2 0_3 ; down
W 0_3 0; down=0.05, 0V
R3 2 3; right
E1 5_2 4_2 fdopamp 3 6 0_4 A; right, mirror, l
W 5_2 5; right
W 4_2 4; right
P2 5 4; down
W 5_1 5_2; down
W 6_1 6; down
W 3 3_1; down
R2 6_1 5_1; right
W 4_2 4_1; down
R4 3_1 4_1; right
W 0 0_4; right=0.4
W 0 0_2; down=0.01, 0V
; draw_nodes=connected
_images/fdopamp-amplifier1.png

opamp-displacement-current-sensor-noise-model1.sch

Vs 6 0_3 ac; down=2
Cs 6 4; right
W 0_3 0; right
E1 1 0 opamp 0_4 2_1 A; right, mirror
W 1 1_2; right=0.5
P 1_2 0_6; down
W 4 4_3; right
Vn 4_3 2 noise; right
W 2 2_1; right=0.5
In 2 0_1 noise; down
W 0_4 0_2; down
W 0 0_5; right
W 0_5 0_1; right
W 0_1 0_2; right
W 0_2 0_6; right=0.5
W 4 4_2; up
VnR 4_2 3 noise {sqrt(4 * k_b * T * R)}; right
R 3 1_1; right
W 1_1 1; down
; draw_nodes=connections, label_nodes=primary
_images/opamp-displacement-current-sensor-noise-model1.png

opamp-displacement-current-sensor1.sch

Vs 3 0_3 ac; down=2
Cs 3 2_1; right
W 0_3 0; right
E1 1 0 opamp 0_4 2 A; right, mirror
W 1 1_2; right=0.5
P 1_2 0_1; down, v=V_o
W 2_1 2; right=0.5
W 0_4 0_2; down
W 0 0_2; right
W 0_2 0_1; right=0.5
W 2 2_2; up
R 2_2 1_1; right
W 1_1 1; down
; draw_nodes=connections, label_nodes=primary
_images/opamp-displacement-current-sensor1.png

opamp-noninverting-amplifier-noisy.sch

NRs 1 _nodeanon1 Rs; down
VnRs _nodeanon1 0 noise {sqrt(4 * k_B * T * Rs)}; down
Vn 1 2 noise; right
W 2 3; right
In1 2 0_2 noise; down, l=I_{n+}
W 0 0_2; right
In2 5 0_5 noise; down, l=I_{n-}
W 5 4; right
W 0_2 0_5; right
W 4 6; down
NR1 6 _nodeanon2 R1; down
VnR1 _nodeanon2 0_6 noise {sqrt(4 * k_B * T * R1)}; down
W 0_5 0_6; right
NR2 6 _nodeanon3 R2; right
VnR2 _nodeanon3 7 noise {sqrt(4 * k_B * T * R2)}; right
W 8 7; down
E 8 0 opamp 3 4 A; right
W 8 9; right
W 0_6 0_9; right
P 9 0_9; down
; draw_nodes=connections, label_nodes=none
_images/opamp-noninverting-amplifier-noisy.png

opamp-piezo-amplifier1.sch

Cs 1 0; down=4
W 1 1_1; right
Rs 1_1 0_1; down=4
W 0 0_1; right
W 1_1 1_2; right=2
Vn 1_2 2 noise; right
E 5_1 0 opamp 2 3_2 A; right
W 3 3_1; right
W 3_1 3_2; right
W 3 3_3; down
R1 3_3 4; down
C 4 0_2; down
W 0_1 0_2; right
W 3_1 3_4; down=1.5
Inn 3_4 0_3 noise; down
W 0_2 0_3; right
W 2 2_1; down=2
Inp 2_1 0_4 noise; down
W 0_3 0_4; right
W 3_3 3_5; right=3
R2 3_5 5_2; right
W 5_1 5_2; down=2
W 5_1 5; right
Po 5 0_5; down, v=v_o
W 0_4 0_5; right
; draw_nodes=connections, label_nodes=none
_images/opamp-piezo-amplifier1.png

opamp-transimpedance-amplifier-with-voltage-gain1.sch

E 1 0 opamp 3 2 Ad; right
W 2_1 2; right
W 2 2_2; down
R1 2_2 4; right
R2 1 4; down
R3 4 4_1; down
W 4_1 0; down=0.01, 0V
W 1 1_1; right
W 3 0; down=0.25, 0V
; draw_nodes=connections, label_ids=none, label_nodes=primary
_images/opamp-transimpedance-amplifier-with-voltage-gain1.png

pierce-oscillator.sch

U1 inverter; right
W 5 U1.in; right=0.5
W U1.out 6; right=0.5
W 6 9; right=0.5
R1 7 8; right
W 5 1; down=0.75
W 6 2; down=0.75
W 5 7; up=0.75
W 6 8; up=0.75
XT1 1 2; right
C1  1 4; down=0.8
C2  2 3; down=0.8
W 4 0; down=0.1, implicit, l=GND
W 3 0; down=0.1, implicit, l=GND
; draw_nodes=connections, label_nodes=False
_images/pierce-oscillator.png

sallen-key-lpf1.sch

P 1 0; down, v_=v_{in}(t)
R1 1 2; right
R2 2 3; right
C1 2 4; up
C2 3 9; down
W 4 5; right
W 5 6; right
W 6 7; down=0
W 7 8; right=0.5
E 7 0 opamp 3 11 A; right, mirror, scale=0.75, size=0.75
W 5 11; down=0.5
P 8 10; down, v^=v_{out}(t)
W 0 9; right
W 9 10; right
;draw_nodes=connections, label_nodes=False, help_lines=1
_images/sallen-key-lpf1.png

multiple-feedback-lpf.sch

R2 1 2 R2; right
R3 2 3 R3; right
C2 2 0_3 C2; down=1.15
E1 6 0_3 opamp 0 3 A; mirror, scale=0.5, size=0.5, l=A
W 0 0_2; down
W 3 3_1; up=0.75
C3 3_1 6_1 C3; right
W 6_1 6; down
W 2 2_1; up=1
R4 2_1 6_2 R4; right
W 6_2 6_1; down
W 6 7; right
W 0_3 0_2; right
W 0_2 0_7; right
W 0_3 0_1; left=1
P1 1 0_1; down
P2 7 0_7; down
; draw_nodes=connections, label_ids=none, label_nodes=primary
_images/multiple-feedback-lpf.png

guard1.sch

Cable1; right=4, dashed, kind=coax
W 1 Cable1.in; right=0.5
W Cable1.out 2; right=0.5
# Provide electrical connection
W Cable1.in Cable1.out; free, invisible
W Cable1.ognd 10; down=0.5
Cc Cable1.mid Cable1.b; down=0.2, dashed, scale=0.6
W 2 3; right=1.5
W 3 11; right=0.5
W 3 4; down=0.5
W 5 6; down=0.5
W 6 7; left
W 7 10; up=0.5
R 10 8; right
E 8 0 opamp 4 5 A; left=0.5, mirror, scale=0.5
; label_nodes=none, draw_nodes=connections
_images/guard1.png

shield-ground.sch

Vs 14 12 ac; down
Rs 14 1; right
Cable1; right=4, dashed, kind=coax, l=
W 1 Cable1.in; right=0.5
W Cable1.out 2; right=0.5
W Cable1.ognd 10; down=0.5
Cc Cable1.mid Cable1.b; down=0.2, dashed, scale=0.6
W 2 11; right=0.75
W 7 10; up=0.5
E2 15 0 opamp 11 17 A_1; right, scale=0.5
W 17 18; down
W 12 7; right
W 7 18; right
W 18 0; down=0.2, sground
Rin 11 17; down
; label_nodes=none, draw_nodes=connections
_images/shield-ground.png

shield-guard.sch

Vs 14 12 ac; down
Rs 14 1; right
Cable1; right=4, dashed, kind=coax, l=
W 1 Cable1.in; right=0.5
W Cable1.out 2; right=0.5
W Cable1.ognd 10; down=0.5
Cc Cable1.mid Cable1.b; down=0.2, dashed, scale=0.6
W 2 3; right=1.5
W 3 11; right=0.75
W 3 4; down=0.5
W 5 6; down=0.5
W 6 7; left
W 7 10; up=0.5
R 10 8; right
E1 8 0 opamp 4 5 A_2; left=0.5, mirror, scale=0.5
E2 15 0 opamp 11 17 A_1; right, scale=0.5
W 17 18; down
W 12 18; right
W 18 0; down=0.2, sground
Rin 11 17; down
; label_nodes=none, draw_nodes=connections
_images/shield-guard.png

opamp-displacement-current-sensor-noise-model1.sch

Vs 6 0_3 ac; down=2
Cs 6 4; right
W 0_3 0; right
E1 1 0 opamp 0_4 2_1 A; right, mirror
W 1 1_2; right=0.5
P 1_2 0_6; down
W 4 4_3; right
Vn 4_3 2 noise; right
W 2 2_1; right=0.5
In 2 0_1 noise; down
W 0_4 0_2; down
W 0 0_5; right
W 0_5 0_1; right
W 0_1 0_2; right
W 0_2 0_6; right=0.5
W 4 4_2; up
VnR 4_2 3 noise {sqrt(4 * k_b * T * R)}; right
R 3 1_1; right
W 1_1 1; down
; draw_nodes=connections, label_nodes=primary
_images/opamp-displacement-current-sensor-noise-model1.png

opamp-displacement-current-sensor1.sch

Vs 3 0_3 ac; down=2
Cs 3 2_1; right
W 0_3 0; right
E1 1 0 opamp 0_4 2 A; right, mirror
W 1 1_2; right=0.5
P 1_2 0_1; down, v=V_o
W 2_1 2; right=0.5
W 0_4 0_2; down
W 0 0_2; right
W 0_2 0_1; right=0.5
W 2 2_2; up
R 2_2 1_1; right
W 1_1 1; down
; draw_nodes=connections, label_nodes=primary
_images/opamp-displacement-current-sensor1.png

opamp-noninverting-amplifier-noisy.sch

NRs 1 _nodeanon1 Rs; down
VnRs _nodeanon1 0 noise {sqrt(4 * k_B * T * Rs)}; down
Vn 1 2 noise; right
W 2 3; right
In1 2 0_2 noise; down, l=I_{n+}
W 0 0_2; right
In2 5 0_5 noise; down, l=I_{n-}
W 5 4; right
W 0_2 0_5; right
W 4 6; down
NR1 6 _nodeanon2 R1; down
VnR1 _nodeanon2 0_6 noise {sqrt(4 * k_B * T * R1)}; down
W 0_5 0_6; right
NR2 6 _nodeanon3 R2; right
VnR2 _nodeanon3 7 noise {sqrt(4 * k_B * T * R2)}; right
W 8 7; down
E 8 0 opamp 3 4 A; right
W 8 9; right
W 0_6 0_9; right
P 9 0_9; down
; draw_nodes=connections, label_nodes=none
_images/opamp-noninverting-amplifier-noisy.png

Transducers¶

KLM2.sch

Cable1; right=2, kind=coax, l=Z_0
W 1 Cable1.in; right=0.5, i=U_b
W Cable1.out 2; right=0.5
W Cable1.ignd 1_0; down=0.5
W 14_0 1_0; right=0.5
Pb 1 14_0; down, v_=F_b

Cable2; right=2, kind=coax, l=Z_0
W 2 Cable2.in; right=0.5
W Cable2.out 3; right=0.5, i<=U_f
W Cable2.ognd 3_0; down=0.5
W 3_0 13_0; right=0.5
Pf 3 13_0; down, v^=F_f

W 2 4; down=1.5
W Cable2.ignd 5; down=0.1
W Cable1.ognd 6; down=0.1
W 6 5; right

TF1 4 7 8 9 phi; right
W 7 10; right=0.5
W 5 10; down

Pe 11 0; down, v_=V
C0 11 12; right, i>^=I
Z 12 8 {j * X_1}; right
W 0 9; right

W 9 7; right, ignore

; draw_nodes=connections, label_nodes=none, label_ids=none
_images/KLM2.png

KLM3.sch

Pb 1 0_1; down, v_=F_b
TLb 2 6 1 0_1 Z_0 {s / c} {d / 2}; right

Pf 3 0_3; down, v^=F_f
TLf 3 0_3 15 5 Z_0 {s / c} {d / 2}; right

W 2 15; right=0.5
W 2 4; down=1.5
W 6 5; right=0.5

TF1 4 7 8 9 phi; right
W 9 7; right=0.5, dashed
W 7 10; right=0.5
W 5 10; down

Pe 11 0; down, v_=V
C0 11 12; right, i>^=I
Z 12 8 {j * X_1}; right
W 0 9; right

W 9 7; right, ignore

; draw_nodes=connections, label_nodes=none, label_ids=none
_images/KLM3.png

accelerometer1.sch

Pm1 1 0_1; down, v=f_1
W 1 0_1; down, dashed
Pm2 2 0_2; down, v=f_2
W 2 0_2; down, dashed
Lm1 1 3; right=3, i>^=u_1
Lm2 3 2; right=3, i^<=u_2
Rm 3 4; down
Cm 4 5; down
TF 5 6 9 0 k; right
W 6 0_6; down
W 0_1 0_10; right
W 0_10 0_6; right, free
W 0_6 0_2; right

Pe 7 0_7; down, v_=v
W 7 8; right=0.5, i=i
W 0_7 0_8; right=0.5
W 8 9; right
W 0_8 0; right
C0 8 0_8; down
W 0 0_10; down, dashed
; label_nodes=none, draw_nodes=connections
_images/accelerometer1.png

Miscellaneous¶

colors1.sch

Sblue_1 box; fill=blue, l=blue
Sblue_2 box; fill=blue!74, l=blue!75
O Sblue_1.e Sblue_2.w; right=0.25
Sblue_3 box; fill=blue!50, l=blue!50
O Sblue_2.e Sblue_3.w; right=0.25
Sblue_4 box; fill=blue!25, l=blue!25
O Sblue_3.e Sblue_4.w; right=0.25
O Sblue_4.e Sviolet_1.w; right=0.25

Sviolet_1 box; fill=violet, l=violet
Sviolet_2 box; fill=violet!74, l=violet!75
O Sviolet_1.e Sviolet_2.w; right=0.25
Sviolet_3 box; fill=violet!50, l=violet!50
O Sviolet_2.e Sviolet_3.w; right=0.25
Sviolet_4 box; fill=violet!25, l=violet!25
O Sviolet_3.e Sviolet_4.w; right=0.25
O Sblue_1.s Spurple_1.n; down=0.25

Spurple_1 box; fill=purple, l=purple
Spurple_2 box; fill=purple!74, l=purple!75
O Spurple_1.e Spurple_2.w; right=0.25
Spurple_3 box; fill=purple!50, l=purple!50
O Spurple_2.e Spurple_3.w; right=0.25
Spurple_4 box; fill=purple!25, l=purple!25
O Spurple_3.e Spurple_4.w; right=0.25
O Spurple_4.e Sred_1.w; right=0.25

Sred_1 box; fill=red, l=red
Sred_2 box; fill=red!74, l=red!75
O Sred_1.e Sred_2.w; right=0.25
Sred_3 box; fill=red!50, l=red!50
O Sred_2.e Sred_3.w; right=0.25
Sred_4 box; fill=red!25, l=red!25
O Sred_3.e Sred_4.w; right=0.25
O Spurple_1.s Sgreen_1.n; down=0.25

Sgreen_1 box; fill=green, l=green
Sgreen_2 box; fill=green!74, l=green!75
O Sgreen_1.e Sgreen_2.w; right=0.25
Sgreen_3 box; fill=green!50, l=green!50
O Sgreen_2.e Sgreen_3.w; right=0.25
Sgreen_4 box; fill=green!25, l=green!25
O Sgreen_3.e Sgreen_4.w; right=0.25
O Sgreen_4.e Steal_1.w; right=0.25

Steal_1 box; fill=teal, l=teal
Steal_2 box; fill=teal!74, l=teal!75
O Steal_1.e Steal_2.w; right=0.25
Steal_3 box; fill=teal!50, l=teal!50
O Steal_2.e Steal_3.w; right=0.25
Steal_4 box; fill=teal!25, l=teal!25
O Steal_3.e Steal_4.w; right=0.25
_images/colors1.png

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